Metal interconnections in very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuits typically consist of interconnect structures containing patterned layers of metal wiring. Typical integrated circuit (IC) devices contain from three to fifteen layers of metal wiring. As feature size decreases and device area density increases, the number of interconnect layers is expected to increase.
The materials and layout of these interconnect structures are preferably chosen to minimize signal propagation delays, hence maximizing the overall circuit speed. An indication of signal propagation delay within the interconnect structure is the RC time constant for each metal wiring layer, where R is the resistance of the wiring and C is the effective capacitance between a selected signal line (i.e., conductor) and the surrounding conductors in the multilevel interconnect structure. The RC time constant may be reduced by lowering the resistance of the wiring material. Copper is therefore a preferred material for IC interconnects because of its relatively low resistance. The RC time constant may also be reduced by using dielectric materials with a lower dielectric constant, k.
Many performance advantages are obtained by using a low-k dielectric material as the inter-level dielectric (ILD) for back-end-of-line (BEOL) interconnects of high speed microprocessors, application specific integrated circuits (ASICs) and related integrated circuit devices. In advanced interconnect structures, the ILD is preferably a low-k polymeric thermoset material such as SiLK™ (an aromatic hydrocarbon thermosetting polymer available from The Dow Chemical Company). Other preferable low-k dielectric materials include carbon-doped silicon dioxide (also known as silicon oxycarbide or SiCOH dielectrics); fluorine-doped silicon oxide (also known as fluorosilicate glass, or FSG); spin-on glasses; silsesquioxanes, including hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and mixtures or copolymers of HSQ and MSQ; and any silicon-containing low-k dielectric.
There are several fabrication advantages when an organic thermoset polymer is selected. The primary advantages of organic thermoset polymer dielectrics are lower dielectric constant (typically about 2.65), lower cracking rate under applied stress, and etch (RIE) selectivity. Glass dielectric materials such as SiCOH or carbon-doped oxide tend to crack under applied stress and in humid atmosphere, while organic thermoset polymers do not. Moreover, the carbon-based thermoset polymers are not etched in the RIE chemistry used to open the cap at the bottom of each via, while silicon-based SiCOH is etched in this etch step. In other words, carbon-based thermoset polymers exhibit high etch selectivity while silicon-based SiCOH exhibits low selectivity. Finally, organic thermoset polymer materials are spin applied, whereas glasses are typically applied using plasma-enhanced chemical vapor deposition (PE CVD) tools. Spin apply tools have lower cost of ownership than PE CVD tools.
However, one disadvantage is the low modulus of organic polymer or low k CVD dielectrics, which can result in defects or breaches formed in the passivation layers when the completed IC chip is electrically connected via wirebonding (or soldering) methods to an IC holder. F or example, cracks may form in the passivation layers in the vicinity of bond pads. Such cracks typically have a width of 1000 angstroms to 5000 angstroms, a depth of several microns, and a length of 1 micron to 100 microns. Cracks often occur as well at the terminal insulator level of the chip. These cracks have many causes; most notable are those caused by rough handling of the finished chip prior to packaging and the damage that can result during the die wire bonding process. Delamination of the passivation layers is also a possible problem.
Although such microcracks may have been present in prior devices using conventional inorganic dielectric materials, the nature of the integration in those devices minimized the deleterious impact of such defects on product reliability. With the advent of low-k dielectrics and their inherent inferior mechanical properties with respect to inorganic oxides, an increase in sensitivity and amount of microcracking at the terminal insulator level of the chip has been observed.
In devices comprising low-k dielectric materials, the terminal insulator level of the chip is often built utilizing an inorganic oxide layer as a moisture barrier. However, this terminal inorganic oxide is more easily damaged than in devices using oxide for all inter-layer dielectric, due to the unique mechanical structure of low-k dielectric integration. Furthermore, as device ground rules continue to decrease, even without the transition to low-k dielectrics, these microcracks and delaminations are likely to become a significant source of device performance degradation if they are left unrepaired before final packaging and encapsulation.
Post wire-bond packaging and encapsulation processes are ineffective in sealing these cracks in the terminal insulator level of the chip. As a result of the lack of seal or repair of these cracks in the terminal insulator level of the chip, electrical degradation in semiconductor chip electrical performance has been observed during temperature and humidity stress testing. For example, U.S. Pat. No. 5,689,089 discloses the use of silicone-based polymers for encapsulation. However, it has been observed that such polymers alone can not provide an effective barrier to moisture ingress.
More complex schemes using new materials in the passivation layers and in the metal bond pads have been proposed. For example, the Wafer Applied Seal for PEM Protection (WASPP), sponsored by The U.S. Army Manufacturing Technology (ManTech) Program, is a high cost multi-layered approach. A spin applied material (such as hydrogen silsesquioxane, HSQ) and a PE CVD applied material (silicon carbide) are used for passivation. Also, two metal layers (gold plus titanium) are added to the bond pad. However, the use of unconventional materials and additional metal layers adds significantly to the cost of the manufacturing process.
Thus, there remains a need in the art for a low-cost method to enhance temperature/humidity/bias performance of semiconductor devices.